1. Field of the Invention
The present invention relates to an open-drain output circuit, or an output circuit having an open drain output terminal.
2. Description of the Related Art
As an output circuit used for a semiconductor device, there is a known output circuit referred to as an open-drain output circuit, such as described in JP-6-268493A, for example. FIG. 6 shows the configuration of a conventional open-drain output circuit. In the conventional output circuit, generally designated at numeral 200, an input signal DATA is fed to a gate of the transistor N21 through an inverter 201. The output circuit 200 delivers an output signal from an output node Dout connecting a resistor R21 and an N-channel transistor N21 in series between a high-potential power source line and a low-potential power source line. The output signal is transmitted to an external device 202 via a signal transmission line 203. The resistor R21 is impedance-matched with the signal transmission line 203 having a delay time tpd.
FIG. 7 shows a timing chart of an operation in the conventional output circuit as described above. When the input signal DATA is at a high level (H-level), the output circuit 200 connects the output node Dout thereof to the high-potential power source line via the resistor R21 by turning OFF the N-channel transistor N21, whereby the output signal assumes a H-level. On the other hand, when the input signal DATA is at a low level (L-level), the output circuit 200 connects the output node Dout thereof to the low-potential power source line via the transistor N21 by turning ON the N-channel transistor N21, whereby the output signal assumes a L-level.
It is to be noted that the potential of the output node Dout of the output circuit 200 does not change to the H-level or L-level immediately after the input signal DATA changes, due to an influence of a signal reflection, etc., and is settled at the H-level or L-level after a significant time interval is elapsed since the signal switching occurred. For example, when the input signal DATA changes from a H-level to a L-level in the case of the input terminal of the external device 202 being open, the signal is totally reflected by the input terminal of the external device 202. This signal reflection causes the potential of the output node Dout of the output circuit 200 to become gradually close to a L-level without immediately lowering to the L-level. The potential of the output node Dout is finally settled at the L-level after the input signal DATA assumes the L-level and the time period in which the signal reciprocates in the signal transmission line 203 elapses, that is, after the time delay of tpd×2 elapses.
In the output circuit 200, when a L-level signal is output, the current continues to flow from the high-potential power source line to the low-potential power source line via the resistor R21 and the transistor N21, with the transistor N21 being turned ON. For example, in FIG. 7, the current continues to flow in periods T1, T4 to T5, and T7, wherein the input signal DATA is at the L-level. In recent years, although the configuration achieving a lower power dissipation is ever required in the semiconductor device, the conventional output circuit 200 has a problem in that the power dissipation thereof is large due to the operating current which continues to flow at the L-level of the output node Dout.